Verilog doesn’t consider it an error to mix signed and unsigned operands it treats them all as unsigned. If all the operands are signed, the result is signed. This doesn’t sound too bad until you learn that in Verilog: Remember, for a signed number, the MSB is 1 for negative numbers and 0 otherwise. Sign extension copies the most significant bit (MSB) to fill the width. For unsigned operands, Verilog simply fills the new bits with zero, but with signed operands, it uses sign extension. Narrower operands are widened until they’re the same width as the widest. It doesn’t matter what the operators are all Verilog cares about is the width of the operands. Verilog uses the width of the widest operand when evaluating an expression. I’ve done my best to accurately distil a rather dry and complex subject into something palatable, so I hope I don’t offend the language lawyers and bore everyone else.Īn expression consists of operands, such as variables and literals, and operators, such as addition and assignment. Now we know how to handle signed vectors and literals, it’s time to wrestle with expressions.

Reg signed s // 8 bit signed vectorĪlways_ff posedge clk) begin if (s < 0) begin // s is negative You can switch the sign of a two’s complement number by inverting the bits and adding one: But what is the two’s complement? The positive and negative two’s complement representations of an N-bit number add up to 2 N.įor example, with four-bit values: 7 is 0111 and -7 is 1001 because 0111 + 1001 = 10000 (2 4).ĭiscarding the extra bit, the result of adding a number and its two’s complement is always zero.

With two’s complement, addition, subtraction, and multiplication all work as they do with positive binary numbers. The standard approach is two’s complement, as with almost all CPUs and software. If your design requires negative values, you need to handle signed numbers. You can nest concat operators, as in the final example above.Ĭoncat allows us to set an appropriate value regardless of the vector width. Localparam CORDW = 12 // coordinate width in bits Let’s take a look at 42 in binary: 101010 2 Simple, right?įor positive integers, things are pretty straightforward. BinaryĬomputers famously “think” in binary, and the same is true for most electronics. How many bits do I need? Do I need signed numbers? Will BCD make my design simpler? Is fixed-point accurate enough? What happens when I mix different widths in one expression?įor something a bit less ordinary, try Cistercian numerals (Wikipedia). We’re so familiar with different representations of numbers we hardly give them a second thought.ĭifferent representations express (almost) the same thing but work better (or worse) in different circumstances: hexadecimal is suitable for a memory address, while scientific notation compactly expresses vast and tiny numbers alike.Īs a hardware designer, you need to consider how you represent numbers. Fixed-Point Numbers - precision without complexity.Multiplication with DSPs - efficient FPGA multiplication.Vectors and Arrays - working with Verilog vectors and arrays.Numbers in Verilog (this post) - introduction to numbers in Verilog.Share your thoughts with on Mastodon or Twitter. In this first post, we consider integers, dig into the challenges of signed numbers and expressions, and then finish with a bit of arithmetic. This series begins with the basics of Verilog numbers, then considers fixed-point, division, square roots and CORDIC before covering more complex algorithms, such as data compression. Welcome to my ongoing series covering mathematics and algorithms with FPGAs.

Convert decimal to binary in verilog